In a large scale digital circuit such as, but not limited to, a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), a number of digital signal processing (DSP) circuit blocks often work together to implement complex tasks. To achieve improved performance, DSP circuit blocks are often operated at high speeds. While FPGA speed, or alternatively the ASIC processing speed, has been improved, one constraint is the propagation delay of signals between two DSP circuit blocks, especially when a random routing distance between the two DSP circuit blocks is encountered, which can be introduced by row based redundancy. When a number of DSP circuit blocks are coupled together, one of the challenges in operating an FPGA is the efficiency of interconnections between the DSP circuit blocks. Once the DSP circuit block has been designed, multiple DSP circuit blocks are coupled together to create a single structure and operated at a high speed, and thus efficient interconnection between the circuit blocks is desired to improve multi-circuit block performance.